This invention relates to systems and methods for equalizing data using a programmable device—e.g., a field-programmable gate array (FPGA) or other programmable logic device (PLD)—in high speed applications.
Programmable devices are well known. Generally, programmable devices, such as FPGAs, contain receiver or transceiver circuitry for processing and recovering incoming signals. However, the speed of such circuitry is often limited by inter-symbol interference (ISI) due to communication channel bandwidth limitations.
Equalizers are used to compensate for amplitude and phase distortion caused by non-ideal communication channels. Typically, two types of equalizers are used to reduce the effects of inter-symbol interference: a continuous-time linear equalizer (CTLE) and a discrete-time equalizer, the latter of which is often implemented as a decision feedback equalizer (DFE).
A CTLE amplifies high-frequency components of an incoming signal to counteract the channel response, which generally attenuates those high-frequency components. A disadvantage of CTLEs, however, is that they also amplify noise at high frequencies. A DFE is therefore used in conjunction with a CTLE to minimize the effects of noise in the incoming signal, and is optimal for larger loss channels where reflection is also present.
A DFE is a non-linear equalizer that reduces inter-symbol interference without introducing additional noise into the signal. Operating a DFE at high data rates is a challenge, however, due to the demanding time requirements of the digital circuitry in the receiver. For example, DFE input sensitivity is especially important in high speed applications due to the significant channel attenuation, which adversely impacts the timing margin. Proper signal offset cancellation, which improves the DFE's input sensitivity, is therefore critical to achieving higher data rates.